library verilog;
use verilog.vl_types.all;
entity RAM_ctrl is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        mem             : in     vl_logic;
        rw              : in     vl_logic;
        address         : in     vl_logic_vector(22 downto 0);
        data_fpga2ram   : in     vl_logic_vector(15 downto 0);
        ready           : out    vl_logic;
        data_ram2fpga_r : out    vl_logic_vector(15 downto 0);
        data_ram2fpga_ur: out    vl_logic_vector(15 downto 0);
        addr            : out    vl_logic_vector(22 downto 0);
        dio             : inout  vl_logic_vector(15 downto 0);
        we_n            : out    vl_logic;
        oe_n            : out    vl_logic;
        ce_n            : out    vl_logic;
        ub_n            : out    vl_logic;
        lb_n            : out    vl_logic;
        clock_ram       : out    vl_logic;
        adv_n           : out    vl_logic;
        cre             : out    vl_logic;
        o_wait          : in     vl_logic
    );
end RAM_ctrl;
